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MIRA Faraday amplifiers
Water Isotopes August 2011
IAEA-TEL-2011-01 proficiency test
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MIRA Faraday amplifiers
MIRA has a detector array composed of 6 Faraday cups located on the focal plane and positioned to collect m/z = 44, 45, 46, 47, 48, and 49. Each cup is individually screened. The signals are collected and amplified using a current to voltage (transimpedance) amplifier with gains of 10^8 (44), 10^10 (45 and 46), 10^12 (47) and 10^13 (48 and 49). Output voltages are in the range 0 to -10V and correspond to maximum beam strengths of 10^-7 amps to 10^-12 amps depending on the gain of each amplifier.
The 10^8 and 10^10 gain amplifiers were designed and built by PFD using a standard transimpedance circuit based on an
AD549 operational amplifier
. These amplifiers have ultra-low input bias currents that can be trimmed to near zero. The gain is controlled by a single precision feedback
. The time constant of the circuit is fixed at ca. 0.1 second (1 Hz bandwidth) by installing a small value (several 10's pF) polyester capacitor in parallel with the feedback resistor. Both corcuit diagrams and PCB layout are shown in Figures 1 and 2.
The high gain (10^12 and 10^13) amplifiers used for the minor isotopologues of CO2 are
models. This amplifier has switchable gain of either 10^12 or 10^13 and switchable time constant of 0.2, 1 and 5 seconds.
The amplifier outputs are inverted and buffered using an unity gain difference amplifier (
) then passed onto a high frequency VFC (
). Note that the VFC devices are configured for a positive input for channels 44, 45 and 46, and for a negative input for channels 47, 48 and 49. This is because the Femto devices output a positive voltage for a positive input current, whilst the home designed amplifier has a negative voltage output for a positive current input.
The clock input to the AD 652 VFC's is provided by a TTL pulse driven by a National Instruments high speed digital I/O unit (9401). This unit operates at the base 40MHz frequency of the host FPGA unit. For the AD 652 a clock speed between 1 and 4 MHz can be chosen giving maximum output frequencies of 500kHz to 2MHz for a 10 volt input signal. Typically a clock frequency of 2MHz is used with a maximum output frequency of 1MHz.
Pulse counting is implemented on the FPGA. The 6 channel counters have a maximum edge detection (loop) frequency of 40MHz. This is significantly faster than the minimum pulse width output from the
which is the same as the clock frequency and ensures no aliasing of the data.
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